(1) Field of the Invention
The present invention generally relates to an ATM (Asynchronous Transfer Mode) switch, and more particularly to an apparatus and method for detecting a fault in an ATM switch.
(2) Description of the Prior Art
Recently, there has been considerable activity in the development of ATM exchanges which realize broad band ISDNs (Integrated Services Digital Networks). Various systems for realizing the ATM systems have been proposed. An example of the proposed systems is a self routing module type switch (hereafter simply referred to as an SRM switch).
The SRM switch has the function of outputting cells input from input highways to output highways. More specifically, switch elements, each having an FIFO (First-in First-Out) memory, are provided at respective cross points of the input and output highways. Each cell has tag data (information indicating a destination output highway of the cell). At each cross point, the tag data of the input cell is compared with an output highway number assigned to each FIFO memory. When the tag data coincides with the output highway number, the input cell is stored in the FIFO memory, and then read out therefrom in response to a read signal applied to the FIFO memory.
FIG. 1 is a block diagram of a conventional ATM switch of the SRM type. The ATM switch shown in FIG. 4 has four input highways HW0-HW3 and four output highways HW0-HW3. As shown, 16 switches SW00-SW33 are provided at respective cross points of the input high ways HW0-HW3 and the output high ways HW0-HW3. It will be noted that the switch "SW12" is positioned at the cross point of the input highway HW1 and the output highway HW2 and functions to transfer the cells via the input highway HW1 to the output highways HW2.
FIG. 2 shows a switch element SW(X,Y) located at a cross point of an input highway HWX (X denotes the input highway number) and an output highway HWY (Y denotes the output highway number). As shown, the switch element SW(X,Y) is composed of a tag comparator (TAG COMP) 50, an FIFO memory 51, a token controller (TOKEN CNT) 52 and a selector (SEL) 53. A token signal separately passes through each of the columns of switch elements. For example, a token signal passes through the switch elements SW00, SW10, SW20 and SW30. When the token controller 52 receives the token signal from the switch SW((X-1),Y) and generates a read control signal when there is any cell in the FIFO memory 51. When there is not any cell, the token controller 52 transfers the received token signal to the switch element SW((X+1),Y). The selector 53 selects, under the control of the token controller 52, either the cell transferred from the switch element SW((X-1),Y) or the cell read out from the FIFO memory 51, and outputs the selected cell to the select switch SW((X+1),Y).
In general, the ATM switch handles cells, each having an identical fixed length. Each cell has a header part used for switching, and an information part (payload part) in which read data to be transferred is stored. In the SRM system, the header part includes switch control data called "tag". The tag data indicates the number of an output highway (output highway number) to which the cell having this tag data is output. Since the ATM switch shown in FIG. 1 has four output highways HW0-HW3, the tag data consists of two bits. Each of the switch elements connected to the same output highway has the same output highway number.
During operation, a cell having the tag data indicating the output highway number Y is received via the input highway having the number X. The received cell is received by the switch element SW(X,Y) shown in FIG. 2. The received cell is input to the tag comparator 50, which receives, from a controller (not shown), the output highway number Y related to the switch element SW(X,Y) shown in FIG. 2. The tag comparator 50 compares the tag data in the received cell with the output highway number Y. Since the tag data shows the output highway number Y, as has been described previously, the tag controller 50 outputs a write signal to the FIFO memory 51. In response to the write signal, the cell is written into the FIFO memory 51.
The switch element SW(X,(Y-1)) positioned on the left side of the switch element SW(X,Y) shown in FIG. 2 receives an output highway number (Y-1) from the controller. Thus, the tag comparator 50 of the switch element SW(X,(Y-1)) does not generate the write signal. Hence, the cell passes through the switch element SW(X,(Y-1)) without being written into the FIFO memory 51 thereof. Each of the switch elements of the ATM switch operates in the same manner as described above.
Since a plurality of FIFO memories are connected to one output highway. If cells are simultaneously read out from some of the FIFO memories, the cells will have a collision with each other. In order to avoid such a collision, the ATM system is designed so that cell data called token or token signal passes through the switch elements in each column. For example, the token signal related to the output highway HW0 is circulated through the switch elements SW00, SW10, SW20, SW30, SW00, . . . in this order.
When the token controller 52 receives the token signal from the switch element SW((X-1),Y), determines whether or not there is any cell in the FIFO memory 51. When it is determined that there is not any cell in the FIFO memory 51, the token controller 52 transfers the received token signal to the token controller 52 of the switch element SW((X+1),Y). When it is determined that there is any cell, the token controller 52 outputs a read signal to the FIFO memory 51. In response to the read signal, one cell is read out from the FIFO memory 51 and applied to the selector 53. At this time, the token controller 52 instructs the cell 53 to select the cell from the FIFO 51. After the cell is output to the switch element SW((X+1),Y), the token controller 52 of the switch element SW(X,Y) transfers the received token signal to the token controller 52 of the switch element SW((X+1),Y).
If a fault occurs in the tag controller 50, a cell which should be written into the FIFO memory 51 will not be written therein or a cell which should not be written into the FIFO memory 51 will be written therein. If a fault occurs in the token controller 52, a cell will be read out from the FIFO memory 51 without receiving the token signal or the token signal is received nevertheless a cell will not be read out therefrom. The above erroneous operations destroys the cells or make the FIFO memory 51 congested with cells. Thus, it is required that the switch elements of the ATM switch be supervised in order to determine whether or not the switch elements operate correctly.
In order to supervise the switch elements, it may be possible to add a parity to each cell and switch the parity-added cell. Thereby, it becomes possible to execute the parity check on the input and output sides of the FIFO memory 51 and the input and output sides of the selector 53. However, it is still impossible to determine whether or not the tag comparator 50 has a fault and determine whether or not the token controller 52 has a fault because there is no change in the parity.